A New CMOS Dynamic Comparator for High-Speed Analog-to-Digital Converters

Abstract

This paper presents a novel CMOS dynamic comparator designed to enhance the performance of high-speed analog-to-digital converters (ADCs). The proposed comparator replaces the traditional back-to-back inverter latch with a dual-input single-output differential amplifier, improving noise immunity, reducing power dissipation, and increasing speed. Five key research questions are explored: noise immunity, power dissipation, speed, circuit area, and robustness against transistor mismatch. The study employs quantitative analysis using Cadence Virtuoso with GPDK 90nm technology to validate the design. Simulation results confirm significant improvements in signal-to-noise ratio, power efficiency, response time, layout compactness, and robustness. The findings suggest that the proposed design advances comparator technology, making it more suitable for high-speed and power-efficient applications. Future work should involve real-world testing and further optimizations to enhance performance.